Core device

The core device is a FPGA-based hardware component that contains a softcore CPU tightly coupled with the so-called RTIO core that provides precision timing. The CPU executes Python code that is statically compiled by the ARTIQ compiler, and communicates with the core device peripherals (TTL, DDS, etc.) over the RTIO core. This architecture provides high timing resolution, low latency, low jitter, high level programming capabilities, and good integration with the rest of the Python experiment code.

While it is possible to use all the other parts of ARTIQ (controllers, master, GUI, dataset management, etc.) without a core device, many experiments require it.

Flash storage

The core device contains some flash space that can be used to store configuration data.

This storage area is used to store the core device MAC address, IP address and even the idle kernel.

The flash storage area is one sector (typically 64 kB) large and is organized as a list of key-value records.

This flash storage space can be accessed by using artiq_coremgmt (see: Core device management tool).

FPGA board ports

All boards have a serial interface running at 115200bps 8-N-1 that can be used for debugging.

Kasli

Kasli is a versatile core device designed for ARTIQ as part of the Sinara family of boards. All variants support interfacing to various EEM daughterboards (TTL, DDS, ADC, DAC…) connected directly to it.

Standalone variants

Kasli is connected to the network using a 1000Base-X SFP module. No-name BiDi (1000Base-BX) modules have been used successfully. The SFP module for the network should be installed into the SFP0 cage. The other SFP cages are not used.

The RTIO clock frequency is 125MHz or 150MHz, which is generated by the Si5324.

DRTIO master variants

Kasli can be used as a DRTIO master that provides local RTIO channels and can additionally control one DRTIO satellite.

The RTIO clock frequency is 125MHz or 150MHz, which is generated by the Si5324. The DRTIO line rate is 2.5Gbps or 3Gbps.

As with the standalone configuration, the SFP module for the Ethernet network should be installed into the SFP0 cage. The DRTIO connections are on SFP1 and SFP2, and optionally on the SATA connector.

DRTIO satellite/repeater variants

Kasli can be used as a DRTIO satellite with a 125MHz or 150MHz RTIO clock and a 2.5Gbps or 3Gbps DRTIO line rate.

The DRTIO upstream connection is on SFP0 or optionally on the SATA connector, and the remaining SFPs are downstream ports.

KC705

An alternative target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST CLOCK and QC2 hardware (FMC).

Common problems

  • The SW13 switches on the board need to be set to 00001.
  • When connected, the CLOCK adapter breaks the JTAG chain due to TDI not being connected to TDO on the FMC mezzanine.
  • On some boards, the JTAG USB connector is not correctly soldered.

VADJ

With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.

NIST CLOCK

With the CLOCK hardware, the TTL lines are mapped as follows:

RTIO channel TTL line Capability
3,7,11,15 TTL3,7,11,15 Input+Output
0-2,4-6,8-10,12-14 TTL0-2,4-6,8-10,12-14 Output
16 PMT0 Input
17 PMT1 Input
18 SMA_GPIO_N Input+Output
19 LED Output
20 AMS101_LDAC_B Output
21 LA32_P Clock

The board has RTIO SPI buses mapped as follows:

RTIO channel CS_N MOSI MISO CLK
22 AMS101_CS_N AMS101_MOSI   AMS101_CLK
23 SPI0_CS_N SPI0_MOSI SPI0_MISO SPI0_CLK
24 SPI1_CS_N SPI1_MOSI SPI1_MISO SPI1_CLK
25 SPI2_CS_N SPI2_MOSI SPI2_MISO SPI2_CLK
26 MMC_SPI_CS_N MMC_SPI_MOSI MMC_SPI_MISO MMC_SPI_CLK

The DDS bus is on channel 27.

NIST QC2

With the QC2 hardware, the TTL lines are mapped as follows:

RTIO channel TTL line Capability
0-39 TTL0-39 Input+Output
40 SMA_GPIO_N Input+Output
41 LED Output
42 AMS101_LDAC_B Output
43, 44 CLK0, CLK1 Clock

The board has RTIO SPI buses mapped as follows:

RTIO channel CS_N MOSI MISO CLK
45 AMS101_CS_N AMS101_MOSI   AMS101_CLK
46 SPI0_CS_N SPI0_MOSI SPI0_MISO SPI0_CLK
47 SPI1_CS_N SPI1_MOSI SPI1_MISO SPI1_CLK
48 SPI2_CS_N SPI2_MOSI SPI2_MISO SPI2_CLK
49 SPI3_CS_N SPI3_MOSI SPI3_MISO SPI3_CLK

There are two DDS buses on channels 50 (LPC, DDS0-DDS11) and 51 (HPC, DDS12-DDS23).

The QC2 hardware uses TCA6424A I2C I/O expanders to define the directions of its TTL buffers. There is one such expander per FMC card, and they are selected using the PCA9548 on the KC705.

To avoid I/O contention, the startup kernel should first program the TCA6424A expanders and then call output() on all TTLInOut channels that should be configured as outputs.

See artiq.coredevice.i2c for more details.

Clocking

The KC705 supports an internal 125MHz RTIO clock (based on its crystal oscillator) and an external clock, that can be selected using the rtio_clock configuration entry. Valid values are i and e, and the default is i. The selected option can be observed in the core device boot logs.

On Kasli, when set to e, the rtio_clock setting overrides the built-in (and variant-dependent) Si5324 synthesizer configuration and disables the Si5324. The user must apply a clock at the RTIO frequency on the Kasli front panel SMA. As the Si5324 is bypassed in this mode, its skew is deterministic, which is useful to distribute clocks externally to Kasli and Urukul when Urukul phase synchronization is desired.